Power electronics

Operation and Design of Single-Phase Grid-Connected Multi-Cascaded-Inverter Using LLC Converter Supplied by a Single Solar Photovoltaic [TMS320F28379D Implementation]

PS: Please download Research Statement Document

You will also find the BOM list of components.

The module-integrated inverter, due to small size and low power rating of the converter, require voltage elevation for grid connection because of the low voltage rating of PV modules (generally around 30V). An advantage of using multilevel converters as PV inverter is related to the output waveforms high quality, reducing the grid connection filter needs, leading to a compact design for low power applications (usually domestic roof-top or for balcony).  This is why AC-module inverters are only found with an additional DC-DC stage, usually with a high frequency transformer to provide galvanic isolation and elevate voltage. Due to the low voltage operation, MOSFET devices are most commonly found in these topologies.

Figure 1: INCEnergy – Single-Phase Grid-Connected Multi-Cascaded-Inverter

Solar power converters benefit greatly of the good characteristics of WBG new devices and a large number of researchers present new developments both based on SiC and GaN devices and the comparison with their counterparts made of silicon is clearly favorable to the new devices [1], [2].

LLC converter – Closed Loop

The PWM signal generation is performed by C2000 Delfino MCUs F28379D LaunchPad Development Kit from Texas Instruments. The microcontroller is a fast instruction fixed-point microprosessor (200MHz). Integrated on-chip peripherals such as serial port, timers, PWM module and peripheral interfaces units make the interfacing task much easier and with higher reliablity.

c2000.jpg

Figure 2: C2000 Delfino MCUs F28379D LaunchPad Development Kit

For analog signal measurement, a 16-channel 10-bit A/D converter with programmable conversion time has been integrated on the CPU. This microcontroller is specially targeted towards industrial drives and servo motor control audiences. Apart from these applications, this part can be utilized to its fullest for solar inverters and converters, digital power, transportation and power line communications. The board shown in Figure 2 is used to develop, debug and execute application programs.

Figure 3: Testing Workbench of Single-Phase Grid-Connected Multi-Cascaded-Inverter [Happly Lab, August 2018]

Table 1. Design Parameters of LLC converter

tabelle

LLC Analog Controller ICE2HS01G

ICE2HS01G is Infineon’s 2nd generation half-bridge LLC controller designed especially for high efficiency half-bridge or full-bridge LLC resonant converter with synchronous rectification (SR) control for the secondary side. The maximum switching frequency is supported up to 1MHz. Apart from the patented SR driving techniques; this IC provides very flexible design and integrates full protection functions as well. It is adjustable for maximum/minimum switching frequency, soft-start time and frequency, dead time between primary switches, turn-on and turn-off delay for secondary SR MOSFETs. The integrated protections include input voltage brownout, primary three-levels over current, secondary over load protection and no-load regulation. It also includes a burst mode function which offers an operation with low quiescent current maintaining high efficiency at low output load while keeping output ripple voltage low.

You can also find the simulation results via FALSTAD.

falstad

LLC1

Figure 4: The input supply of LLC converter

LLC2

Figure 5: ICE2HS01G is Infineon’s 2nd generation half-bridge LLC controller

LLC3

Figure 6: PCB Layout of the whole system

Furthermore, focus is put on the control of power electronic circuits, measuring and protection circuits, and the microcontroller. On the other hand, the auxiliary circuits are all designed and included, in order to make operational prototypes. The control system algorithm is performed using the MATLAB Simulink® model. The parameter values of the PID controllers of the system gains and the compensators are derived using this model. The AC voltage regulation is needed because of the non-linear loads.

5

Figure 7: 3D of LLC Converter

The entire control system is verified on a single-phase pulse-width-modulation (PWM) converter simulation with a simple DSP-based digital implementation of multi-cascade inverter. The controllers for stand-alone inverter are also tested under non-linear conditions (10Ω resistive load, 1mH inductive load and 75mF capacitive load). The PV system controllers consist of two stages, one is for the closed loop control Maximum Power Point Tracking (MPPT) of the DC-DC stage and the other for the closed loop control of the DC-AC stage.

Figure 8: The PCB layout and circuit design of inverter by Eagle

1

Figure 9: The circuit of Gate Driver (IR21834S) for PH-A designed by Eagle

2

Figure 10: The circuit of Gate Driver (IR21834S) for PH-B designed by Eagle

3

Figure 11: The circuit of LM1117MP-ADJ for +5V Output

4

Figure 12: The circuit of ACS712 Current Sensor for Ph-A

This project has presented the modeling of a stand-alone PV system using a special hybrid PWM method. The details of the modeling technique and circuitry simulations were described. The objective of this method is to fit the mathematical equations to the system and validate with circuitry simulation for the purpose of comparison. Analysis of the results shows that the model yields the similar performance as produced by the circuitry simulation.

  • The TMS320F28379D and other ICs were used to maximize reliability, minimize complexity, minimize size (reduced PCB space) and minimize cost.
  • A brief introduction on inverter that includes an overview of inverter power circuit topology, switching strategy and modulation technique has been presented.
  • To verify the operations of grid-connected inverter, a simulation system based on a single-phase 2-level VSI is set up and the simulation is carried out in MATLAB / Simulink and PLECS environment.

Moreover, LLC resonant half-bridge converter design example will be tested considering the parameters like total harmonic distortion and losses. The switching frequency will be altered from 1kHz to 20kHz to achieve best results.  Finally, the sensitivity to ripple in voltage and current at the terminals of the PV module were considered.

Acknowledgment

The author of this paper would like to express their appreciation and sincere gratitude to Austrian Institute of Technology (A.I.T) for providing funding for this project.

APPENDIX A – C CODE

SOGI PLL Code

 #include"math.h"

float u;     // input signal

float sampling = 0.0001 // sampling period [s]

float k = 1.0;    // SOGI OSG band width

float y = 0.0;    // SOGI Output

float y2 = 0.0;  // SOGI Orthogonal output

float omega = 2.0 * 3.14159265 * 50.0 // Grid Frequency [Rad/s]

float theta_g = 0.0; // Estimated Grid Phase Angle

float sin, cos;

float q;

float omega_g = 0.0;  // Initial estimated grid frequency [Rad/s]

float pi_error;

float pi_kp = 1.0    // Proportional gain of PI Controller

float pi_ki = 1.0     // Integral gain of PI Controller

float pi_integrator = 0.0;

// Sogi OSG Calculations:

{ 
error = u-y;

y +=  ((error * k - y2) * omega) * sampling;

y2 += y * omega * sampling;

// Park Transformation

sin = sin(theta_g);

cos = cos(theta_g);

q = -sin * y + cos * y2;

// PI Controller Calculation

pi_error = 0.0 - q;

pi_integrator += pi_error * pi_ki;

omega_g = pi_integrator + pi_kp * pi_error;

// Integrator Calculation

theta_g += omega_g*sampling;

}

// end of code

Code for 3 Outputs

#define                 __REF_SIN_MAX_VAL                       1023
#define                 __REF_SIN_MAX_DIV_2                    (__REF_SIN_MAX_VAL / 2)
#define                 __REF_SIN_MAX_DIV_7                    (__REF_SIN_MAX_DIV_2 / 7)

//

#define                 __REF_POS_LVL1                                               (__REF_SIN_MAX_DIV_2 +(__REF_SIN_MAX_DIV_7))

#define                 __REF_POS_LVL2                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 2))

#define                 __REF_POS_LVL3                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 3))

#define                 __REF_POS_LVL4                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 4))

#define                 __REF_POS_LVL5                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 5))

#define                 __REF_POS_LVL6                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 6))

#define                 __REF_POS_LVL7                                               (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_7 * 7))

//

#define                 __REF_NEG_LVL1                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7))

#define                 __REF_NEG_LVL2                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 2))

#define                 __REF_NEG_LVL3                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 3))

#define                 __REF_NEG_LVL4                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 4))

#define                 __REF_NEG_LVL5                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 5))

#define                 __REF_NEG_LVL6                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 6))

#define                 __REF_NEG_LVL7                                               (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_7 * 7))

//

int Adc_Val; // Reference sinus value

//

int t0 , t1 , t2 , t3 , t4 , t5 , t6 , t7 , t8 , t9;

int s0 , s1 , s2 , s3 , s4 , s5;

int Adc_Tri , Tri_P , Tri_N;

//

int Sin_Inv_1;

//———————————————————————————————————————————-

// Reference sinus readings, PLL output

Adc_Val = 0;

if             (x1 > 0.5)

{

Adc_Val = Adc_Val | 0x0001;

}

if             (x2 > 0.5)

{

Adc_Val = Adc_Val | 0x0002;

}

if             (x3> 0.5)

{

Adc_Val = Adc_Val | 0x0004;

}

if             (x4> 0.5)

{

Adc_Val = Adc_Val | 0x0008;

}

if             (x5> 0.5)

{

Adc_Val = Adc_Val | 0x0010;

}

if             (x6> 0.5)

{

Adc_Val = Adc_Val | 0x0020;

}

if             (x7> 0.5)

{

Adc_Val = Adc_Val | 0x0040;

}

if             (x8> 0.5)

{

Adc_Val = Adc_Val | 0x0080;

}

if             (x9> 0.5)

{

Adc_Val = Adc_Val | 0x0100;

}

if             (x10> 0.5)

{

Adc_Val = Adc_Val | 0x0200;

}

//———————————————————————————————————————————-

// Triangle readings

Adc_Tri = 0;

if             (x11 > 0.5)

{

Adc_Tri = Adc_Tri | 0x0001;

}

if             (x12 > 0.5)

{

Adc_Tri = Adc_Tri | 0x0002;

}

if             (x13> 0.5)

{

Adc_Tri = Adc_Tri | 0x0004;

}

if             (x14> 0.5)

{

Adc_Tri = Adc_Tri | 0x0008;

}

if             (x15> 0.5)

{

Adc_Tri = Adc_Tri | 0x0010;

}

if             (x16> 0.5)

{

Adc_Tri = Adc_Tri | 0x0020;

}

if             (x17> 0.5)

{

Adc_Tri = Adc_Tri | 0x0040;

}

if             (x18> 0.5)

{

Adc_Tri = Adc_Tri | 0x0080;

}

if             (x19> 0.5)

{

Adc_Tri = Adc_Tri | 0x0100;

}

if             (x20> 0.5)

{

Adc_Tri = Adc_Tri | 0x0200;

}

Adc_Tri = Adc_Tri / 8;

Adc_Tri = Adc_Tri + 512;

//

Tri_P =  Adc_Tri;

Tri_N = -Adc_Tri + 1024;

//———————————————————————————————————————————-

// 50Hz comparisons, outputs y5, y6,

if             (Adc_Val < __REF_POS_LVL3  &&  Adc_Val > __REF_NEG_LVL3)

{

y5 = 0;

y6 = 0;

}

else        if             (Adc_Val >= __REF_POS_LVL3)

{

y5 = 1;

y6 = 0;

}

else        if             (Adc_Val <= __REF_NEG_LVL3)

{

y5 = 0;

y6 = 1;

}

else

{

}

//———————————————————————————————————————————-

// 150Hz comparisons, outputs y3, y4,

if             ((Adc_Val > __REF_POS_LVL1  &&  Adc_Val <= __REF_POS_LVL3) || (Adc_Val >= __REF_POS_LVL5))

{

y3 = 1;

y4 = 0;

}

else        if             ((Adc_Val <= __REF_POS_LVL1 && Adc_Val >= __REF_NEG_LVL1) || (Adc_Val < __REF_POS_LVL5 && Adc_Val > __REF_POS_LVL3) || (Adc_Val < __REF_NEG_LVL3 && Adc_Val > __REF_NEG_LVL5))

{

y3 = 0;

y4 = 0;

}

else        if             ((Adc_Val < __REF_NEG_LVL1  &&  Adc_Val >= __REF_NEG_LVL3) || (Adc_Val <= __REF_NEG_LVL5))

{

y3 = 0;

y4 = 1;

}

else

{

}

//———————————————————————————————————————————-

// Inverter control

if            ((Adc_Val < __REF_POS_LVL1)  &&  (Adc_Val > __REF_NEG_LVL1))

{                    /* Term 0 */

t0 = 1;

}

else        if             ((Adc_Val < __REF_POS_LVL5) && (Adc_Val >= __REF_POS_LVL3))

{            /* Term 1 */

t1 = 1;

}

else if     ((Adc_Val <= __REF_NEG_LVL3) && (Adc_Val > __REF_NEG_LVL5))

{            /* Term 2 */

t2 = 1;

}

else if     ( Adc_Val < __REF_POS_LVL3 && Adc_Val >= __REF_POS_LVL1)

{   /* Term 3 */

t3 = 1;

}

else if     ( Adc_Val >= __REF_POS_LVL5)

{                                    /* Term 4 */

t4 = 1;

}

else if     (Adc_Val <= __REF_NEG_LVL1 && Adc_Val > __REF_NEG_LVL3)

{            /* Term 5 */

t5 = 1;

}

else if     ( Adc_Val <= __REF_NEG_LVL5 )

{                                    /* Term 6 */

t6 = 1;

}

//

if            (Adc_Val > __REF_NEG_LVL3 && Adc_Val < __REF_POS_LVL3 )

{

t7 = 1;

s3 = 1;

}

else if     (Adc_Val >= __REF_POS_LVL3 )

{

t8 = 1;

s4 = 1;

}

else if      (Adc_Val <= __REF_NEG_LVL3 )

{

t9 = 1;

s5 = 1;

}

//

/* State */

s0 = (t0 | t1 | t2);

s1 = (t3 | t4);

s2 = (t5 | t6);

s0 *= 0;

s1 *=  (__REF_POS_LVL2 – __REF_SIN_MAX_DIV_2);

s2 *=  (__REF_NEG_LVL2 – __REF_SIN_MAX_DIV_2);

s3 *= 0;

s4 *=  (__REF_POS_LVL4 – __REF_SIN_MAX_DIV_2);

s5 *=  (__REF_NEG_LVL4 – __REF_SIN_MAX_DIV_2);

/* sampled sinus */

Sin_Inv_1 = Adc_Val – (s0 + s1 + s2 + s3 + s4 + s5);

//

if            (Sin_Inv_1 >= __REF_SIN_MAX_DIV_2)

{

/* sinus is on positive directory */

if    (Sin_Inv_1 >= Tri_P )

{

y1 = 1;

y2 = 0;

}

else

{

y1 = 0;

y2 = 0;

}
}
else
{
/* sinus is on negative directory */

if    (Sin_Inv_1 <= Tri_N )

{

y1 = 0;

y2 = 1;

}

else

{

y1 = 0;

y2 = 0;

}

}

//———————————————————————————————————————————-

y7 = Sin_Inv_1;

y8 = Tri_P;

//———————————————————————————————————————————-

Code for 2-OUTPUTS

#define __REF_SIN_MAX_VAL 1023 // peak value
#define __REF_SIN_MAX_DIV_2 (__REF_SIN_MAX_VAL / 2) // Zero value of sinus
#define __REF_SIN_MAX_DIV_ (__REF_SIN_MAX_DIV_2 / 2) //  + and  – middle points
//
//#define __REF_POS_LVL1 (__REF_SIN_MAX_DIV_2 + (__REF_SIN_MAX_DIV_))
#define __REF_POS_LVL1 512 + 128
//
//#define __REF_NEG_LVL1 (__REF_SIN_MAX_DIV_2 – (__REF_SIN_MAX_DIV_))
#define __REF_NEG_LVL1 512 – 128

int Adc_Val; // Ref sinus value
//
int t0 , t1 , t2 , t3 , t4 , t5 , t6 , t7 , t8 , t9;
int s0 , s1 , s2 , s3 , s4 , s5;
int Adc_Tri , Tri_P , Tri_N;
//
int Sin_Inv_1;
//———————————————————————————————————————————-
// Ref sin. readings, PLL output,
Adc_Val = 0;
//
if (x1 > 0.5)
{
Adc_Val = Adc_Val | 0x0001;
}
//
if (x2 > 0.5)
{
Adc_Val = Adc_Val | 0x0002;
}
//
if (x3> 0.5)
{
Adc_Val = Adc_Val | 0x0004;
}
//
if (x4> 0.5)
{
Adc_Val = Adc_Val | 0x0008;
}
//
if (x5> 0.5)
{
Adc_Val = Adc_Val | 0x0010;
}
//
if (x6> 0.5)
{
Adc_Val = Adc_Val | 0x0020;
}
//
if (x7> 0.5)
{
Adc_Val = Adc_Val | 0x0040;
}
//
if (x8> 0.5)
{
Adc_Val = Adc_Val | 0x0080;
}
//
if (x9> 0.5)
{
Adc_Val = Adc_Val | 0x0100;
}
//
if (x10> 0.5)
{
Adc_Val = Adc_Val | 0x0200;
}
//———————————————————————————————————————————-
// Triangle readings
Adc_Tri = 0;
//
if (x11 > 0.5)
{
Adc_Tri = Adc_Tri | 0x0001;
}
//
if (x12 > 0.5)
{
Adc_Tri = Adc_Tri | 0x0002;
}
//
if (x13> 0.5)
{
Adc_Tri = Adc_Tri | 0x0004;
}
//
if (x14> 0.5)
{
Adc_Tri = Adc_Tri | 0x0008;
}
//
if (x15> 0.5)
{
Adc_Tri = Adc_Tri | 0x0010;
}
//
if (x16> 0.5)
{
Adc_Tri = Adc_Tri | 0x0020;
}
//
if (x17> 0.5)
{
Adc_Tri = Adc_Tri | 0x0040;
}
//
if (x18> 0.5)
{
Adc_Tri = Adc_Tri | 0x0080;
}
//
if (x19> 0.5)
{
Adc_Tri = Adc_Tri | 0x0100;
}
//
if (x20> 0.5)
{
Adc_Tri = Adc_Tri | 0x0200;
}
//
Adc_Tri = Adc_Tri / 2;
Adc_Tri = Adc_Tri + 512;
//
Tri_P = Adc_Tri;
Tri_N = -Adc_Tri + 1024;
//———————————————————————————————————————————-
// 50Hz comparisons, outputs y3, y4,
if (Adc_Val < __REF_POS_LVL1 && Adc_Val > __REF_NEG_LVL1)
{
y3 = 0;
y4 = 0;
}
else if (Adc_Val >= __REF_POS_LVL1)
{
y3 = 1;
y4 = 0;
}
else if (Adc_Val <= __REF_NEG_LVL1)
{
y3= 0;
y4 = 1;
}
else
{
}
//———————————————————————————————————————————-
// Inverter control
if ( Adc_Val >= __REF_SIN_MAX_DIV_2)
{ /* Term 4 */
t4 = 1;
}

else if ( Adc_Val <= __REF_SIN_MAX_DIV_2)
{ /* Term 6 */
t6 = 1;
}

/* State */
//__REF_SIN_MAX_DIV_2
s1 = t4 * (__REF_POS_LVL1 – __REF_SIN_MAX_DIV_2);
s2 = t6 * (__REF_NEG_LVL1 – __REF_SIN_MAX_DIV_2);
/* sampled sinus */
Sin_Inv_1 = Adc_Val – (s1 + s2);
//
if (Adc_Val >= __REF_SIN_MAX_DIV_2)
{
/* sinus is on positive directory */
if (Sin_Inv_1 >= Tri_P )
{
y1 = 1;
y2 = 0;
}
else
{
y1 = 0;
y2 = 0;
}
}
else
{
/* sinus is on negative directory */
if (Sin_Inv_1 <= Tri_N )
{
y1 = 0;
y2 = 1;
}
else
{
y1 = 0;
y2 = 0;
}
}
//———————————————————————————————————————————-
// Outputs
y5 = Sin_Inv_1;
y6 =Tri_P;
//y6 = Tri_N;

References

[1] J. Rabkowski, D. Peftitsis and H. P. Nee, „Silicon Carbide Power Transistors: A New Era in Power Electronics Is Initiated,“ IEEE Industrial Electronics Magazine, vol.6, no.2, pp.17-26, June 2012.

[2] R. Singh and M. Pecht, „Commercial impact of silicon carbide,“ IEEE Industrial Electronics Magazine, vol.2, no.3, pp.19-31, Sept. 2008.

[3] https://www.infineon.com/dgdl/ICE2HS01G_PDS_v2.1_20110524_Public.pdf?folderId=db3a304412b407950112b408e8c90004&fileId=db3a30432a40a650012a458289712b4c.

[4]https://www.infineon.com/dgdl/Application_Note_Resonant+LLC+Converter+Operation+and+Design_Infineon.pdf?fileId=db3a30433a047ba0013a4a60e3be64a1.